• Synthesis is an automatic method of converting a higher level of abstraction (RTL) to a lower level of abstraction (gate level netlists).
• Synthesis produces technology-specific implementation from technology-independent VHDL description.
• Not all VHDL can be used for synthesis. There are the VHDL subset for synthesis and synthesis style description.
• Synthesis is very sensitive to how the VHDL code is written!
• Gate level net lists are optimized for area, speed, power, or testability.
• The essence of RTL is that you define all the registers in the system and the transfers between those registers that occur on each clock cycle (i.e., the combinational logic).
• Registers are described either:
1. explicitly through component instantiation, or
2. implicitly through inference (following a few simple rules)
• Combinational logic is described by: sequential control statements, subprograms, or concurrent statements.
• RTL synthesis describes the behavior of system at each clock period.
• RTL synthesis is used for synchronous design.
• An RTL architecture can be divided into a data path and control:
– Data path: performs operations on data (i.e., ALU),
– Control: tells data path, memory, etc. what to do.
• The data path flows left to right, whereas the control flows bottom up.
• Critical path: critical timing path in a logical circuit is the longest sensitizable path from primary inputs to primary outputs.
• The critical path in the circuit limits the maximum clock frequency.
• Synthesis tools examine all signal paths and spot the critical path.
It is recommended to use RTL code whenever possible as it provides the following:
1. Readable code
2. Ability to use same code for synthesis and simulation
3. Portable code for migration to different technologies
4. Reusable code for later designs
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