VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) is one of the industry standard-hardware description languages. The goals of this handout are to provide some basic features of the VHDL language and its use in specifying and simulating digital systems. VHDL features can be learned similar to any other programming languages such as C.
However, the topics will be presented in all the modules and in the laboratories from a design perspective rather than a language theory perspective. VHDL models of simple circuits will be used to introduce features of the language.
VHDL is a language to describe digital systems. VHDL captures the basic fundamentals and concepts of digital systems. Therefore, learning it will reinforce the theory of digital system design. Additionally, VHDL (along with Verilog) is used as a standard description for communication between different design automation (CAD) tools. VHDL is currently used to specify, simulate and synthesize digital systems. The relationship between VHDL model and actual hardware as shown in Figure 1 focuses on the specification and simulation features of the language. The VHDL model is executed by a program called simulator and the resulting waveforms are obtained as shown in Figure 1(a). A simulator runs the VHDL description with specified inputs and generates the output waveforms of the model as a function of time. If the VHDL model accurately represents actual hardware shown in Figure 1(b), then the input/output behavior of the VHDL model must match that of the hardware. If the input stimuli for the VHDL model and the actual hardware are identical, then the resulting outputs should also be identical as shown in Figure 1.
VHDL is also a synthesis language. CAD tools called synthesizers take VHDL descriptions as input. Using the logic implied or described in these models, synthesizers will (a) optimize logic, and (b) map the logic the VHDL code to a target implementation technology as shown in Figure 2. In this course, we will use Xilinx FPGAs as the target implementation technology. It is very important that the VHDL model is properly specified and simulated prior to the synthesis. This is an important step as the synthesis is a computationally intensive step, particularly, for large designs.
Figure 3 encapsulates major features of VHDL. A single component model consists of one entity and one or more architectures. The entity describes the interface of the digital circuit. At a component level the entity describes the pins (ports). The architecture describes the function of the logic circuit either at a behavioral level (data flow or sequential) or at a structural (component) level.
A package can be used to provide a collection of common declarations and other features for a group of entities and architectures (similar to header files and packages in C). Generics is a method of passing information from external environment (similar to passing static parameter values in C).
The problem that we will be using to illustrate some basic features of the language is a home alarm system described below.
ALARM CIRCUIT SPECIFICATION
Design a home alarm circuit that will generate an ALARM output of 1 if the PANIC input is 1 (panic button is pressed), or if the ENABLE input is 1 (system is enabled), EXITING input is 0, and the house is not secure. The house is secure if the WINDOW, DOOR, and GARAGE inputs are all 1 (windows, garage and doors are closed). You can assume that the sensors and or buttons are used to generate WINDOW, PANIC, EXITING, GARAGE,
DOOR and ENABLE signals.
Figures 4(a), 4(b) and 4(c) show the symbolic, schematic and a VHDL representation of the
library IEEE;
use ieee.std_logic_1164.all;
entity alarm_ckt is
-- Port declarations
port
( DOOR, WINDOW: in STD_LOGIC;
GARAGE : in STD_LOGIC;
EXITING, PANIC: in STD_LOGIC;
ALARM : out STD_LOGIC);
end entity alarm_ckt;
-- Body of the alarm circuit
architecture behav of alarm_ckt is
-- Declarative part
signal secure;
begin
-- Statement part
secure <= window and door and garage; alarm <= panic or (enable and (not exiting) and (not secure); end architecture behav; Figure 4(c). A VHDL model of the alarm circuit shown in 4(a) and 4(b)
The VHDL model shown in Fig 4© comprises of an entity (interface) and its architecture (body). The interface specifies the communication of the model with the external world such as the signals that flow into and out of the black box that is represented by the entity. Note the similarities between the entity and symbolic model shown in Fig 4(a). The body (architecture) describes the details of the digital system and how the output changes to variations of the inputs. Thus there is a clear separation in the VHDL model in the specification and implementation. Specifications provide the function to be implemented (identifier) and how the design should communicate with the external world. For example, the specification of the alarm circuit is the entity description of Figure 4©. A number of solutions are feasible for the alarm specification each trading one or more of the following features: cost, speed, reliability, power, etc. Some other implementations of alarm circuit will be presented in later modules. In the next few sections the details (syntax) of the entity and architecture are provided. New features of VHDL are presented as we continue through these sections.
INTERFACE
The interface of the alarm circuit is repeated below
entity alarm_ckt is
· Port declarations
port (DOOR, WINDOW, GARAGE : in STD_LOGIC;
EXITING, PANIC: in STD_LOGIC;
ALARM : out STD_LOGIC);
library IEEE;
use ieee.std_logic_1164.all;
entity alarm_ckt is
· Port declarations
port
( DOOR, WINDOW: in STD_LOGIC;
GARAGE : in STD_LOGIC;
EXITING, PANIC: in STD_LOGIC;
ALARM : out STD_LOGIC); end entity alarm_ckt;
· Body of the alarm circuit
architecture behav of alarm_ckt is
· Declarative part
signal secure;
begin
· Statement part
secure <= window and door and garage; alarm <= panic or (enable and (not exiting) and (not secure); end architecture behav; end entity alarm_ckt; The interface consists of the entity declaration. The header of the entity declaration starts with the keyword entity, followed by the name of the design entity, and followed by the keyword is. Entity declaration closes with the keyword end, followed by an optional keyword entity, followed by the optional entity name. The entity declaration is terminated by a semicolon. The design entity name is an identifier. An identifier may be of any length and is case insensitive. The first character must be a letter and the last character must not be an underscore and can comprise of alphanumeric characters and underscore ( _ ). Lines beginning with two dashes “—“ are comments. Comments can be placed any where within the VHDL code.
The keyword port is used in port declarations. Port declarations are used to specify the name, mode (direction), and type of signals that flow in/out of the design entity. Three commonly used modes of ports are in (input), out (output), and inout (input/output).The type of the port defines the legal values that are allowed at the port. For the time being we will be restricting to bit, std_logic (0 or 1 as values), and Boolean (TRUE or FALSE) data types.
VHDL is a very strongly typed language. Therefore, the port signals data type must match with the signals assigned to the port.
ARCHITECTURE
Following the interface of the alarm circuit, we will look into the body described following.
· Body of the alarm circuit architecture behav of alarm_ckt is
· Declarative part signal secure;
begin
· Statement part
secure <= window and door and garage; alarm <= panic or (enable and (not exiting) and (not secure); end architecture behav; The header of the body begins with the keyword architecture, followed by the architecture name (identifier), followed by the keyword of, followed by the identifier of the design entity, and followed by the key word is. The last statement of the body consists of the keyword end, followed optionally by the keyword architecture and the identifier of the architecture. The architecture primarily consists of two parts: declarative part and statement part. Declarative part declares the data types of objects that are local to the body. Note once again that VHDL is strongly typed. Therefore, all objects must have their data type declared before they are used in the statements. The declarative part effectively extends the header of the architecture to the keyword begin. LOGIC OPERATIONS AND PRECEDENCE VHDL provides a set of predefined logical operators as described below OPERATOR DEFINITION
and conjunction
or disjunction
not complement
nor complement disjunction
nand complement conjunction
xor exclusive disjunction
xnor complement exclusive disjunction
not is a unary operation where as all other logical operations are all binary. The operators in an expression are executed starting from left to right in the order in which they appear. VHDL operators are evaluated in an order determined by the operator precedence. Operators of higher precedence are evaluated before the lower ones. not operator has a higher precedence over all other operators. All other binary operators have equal precedence (different from Boolean logic). Parentheses can be used to control the operator execution.
CONCURRENCY
The assignment statements used in the VHDL model of Figure 4© are called concurrent signal assignment statements. Unlike the assignments done in software programming languages that get executed in a sequential manner, these VHDL signal assignment statements are executed concurrently. The statements get executed whenever a signal value on the right hand side (RHS) of the assignment statement change. There is no implied or explicit procedural flow of control. To visualize this let us look at the logic circuit implemented by the two assignment statements and given in Figure 4©. Thus the concurrent signal assignment statements mimic the nonprocedural characteristics of hardware; the hardware components operate in parallel and will be active whenever one of the inputs of the component changes. The order in which concurrent signal statements are written has no effect on the order in which they execute.
The signal declaration used in the declaration section of the body of the VHDL model starts with the keyword signal followed by the name (identifier) of the signal and its data type. Unlike ports signals do not have a mode or direction of signal flow. A signal in effect represents a wire used to connect logic components. The next two sections illustrate some of the language elements and their organization. Although this deviates from our scheme of presenting VHDL with a design perspective, it provides a good overall description of the organization of the language.
DESIGN UNITS AND LIBRARIES
VHDL language organization is better described in the pyramid structure shown in Figure 5. At the base of the pyramid are the user defined data types and since VHDL is a strongly typed language this forms the foundation. Objects such as signals hold values for the defined data types. Expressions transform or combine operations with these objects. Typically expressions can be viewed as statements within the model. Statements are contained within design units such as entities and architectures. Finally these design units are contained within libraries.
There are five kinds of design units within the VHDL language and they can be categorized as primary and secondary design units.
· Primary design units
1. Entity
2. Package
3. Configuration
· Secondary design units
1. Architectural Body
2. Package Body
Figure 6 illustrates the process of creating a design unit from a textual VHDL models. All design units are stored in libraries. A VHDL compiling and simulating environment typically has a VHDL analyzer, a source-level debugger, a result viewer, and other utilities. A VHDL design file comprises of one or more design entities or units. VHDL analyzer checks the correctness of syntax of the design file. It compiles the textual VHDL code in an intermediate form that is accepted by the VHDL simulator and/or synthesizer. These compiled design units are stored in a design library. The designer specifies one of the design libraries as the WORK library. The compiled unit is stored in the WORK library. The designer can change the mapping of the WORK library. The design environment also provides a library called STD which consists of two predefined packages: STANDARD and TEXTIO. In addition most of the design environments also provide the IEEE standard library which is based on a nine-valued logic, the IEEE standard 1164.
Once all the design units in a complete design are compiled, a top-level design entity or its configuration file is selected for simulation. If simulations thoroughly verify the functioning of design, the VHDL model can be provided as input to synthesizer. The synthesis tool maps the VHDL functionality onto physical hardware or a possible logic circuit that can be physically built as shown in Figure 7
However, the topics will be presented in all the modules and in the laboratories from a design perspective rather than a language theory perspective. VHDL models of simple circuits will be used to introduce features of the language.
VHDL is a language to describe digital systems. VHDL captures the basic fundamentals and concepts of digital systems. Therefore, learning it will reinforce the theory of digital system design. Additionally, VHDL (along with Verilog) is used as a standard description for communication between different design automation (CAD) tools. VHDL is currently used to specify, simulate and synthesize digital systems. The relationship between VHDL model and actual hardware as shown in Figure 1 focuses on the specification and simulation features of the language. The VHDL model is executed by a program called simulator and the resulting waveforms are obtained as shown in Figure 1(a). A simulator runs the VHDL description with specified inputs and generates the output waveforms of the model as a function of time. If the VHDL model accurately represents actual hardware shown in Figure 1(b), then the input/output behavior of the VHDL model must match that of the hardware. If the input stimuli for the VHDL model and the actual hardware are identical, then the resulting outputs should also be identical as shown in Figure 1.
VHDL is also a synthesis language. CAD tools called synthesizers take VHDL descriptions as input. Using the logic implied or described in these models, synthesizers will (a) optimize logic, and (b) map the logic the VHDL code to a target implementation technology as shown in Figure 2. In this course, we will use Xilinx FPGAs as the target implementation technology. It is very important that the VHDL model is properly specified and simulated prior to the synthesis. This is an important step as the synthesis is a computationally intensive step, particularly, for large designs.
Figure 3 encapsulates major features of VHDL. A single component model consists of one entity and one or more architectures. The entity describes the interface of the digital circuit. At a component level the entity describes the pins (ports). The architecture describes the function of the logic circuit either at a behavioral level (data flow or sequential) or at a structural (component) level.
A package can be used to provide a collection of common declarations and other features for a group of entities and architectures (similar to header files and packages in C). Generics is a method of passing information from external environment (similar to passing static parameter values in C).
The problem that we will be using to illustrate some basic features of the language is a home alarm system described below.
ALARM CIRCUIT SPECIFICATION
Design a home alarm circuit that will generate an ALARM output of 1 if the PANIC input is 1 (panic button is pressed), or if the ENABLE input is 1 (system is enabled), EXITING input is 0, and the house is not secure. The house is secure if the WINDOW, DOOR, and GARAGE inputs are all 1 (windows, garage and doors are closed). You can assume that the sensors and or buttons are used to generate WINDOW, PANIC, EXITING, GARAGE,
DOOR and ENABLE signals.
Figures 4(a), 4(b) and 4(c) show the symbolic, schematic and a VHDL representation of the
library IEEE;
use ieee.std_logic_1164.all;
entity alarm_ckt is
-- Port declarations
port
( DOOR, WINDOW: in STD_LOGIC;
GARAGE : in STD_LOGIC;
EXITING, PANIC: in STD_LOGIC;
ALARM : out STD_LOGIC);
end entity alarm_ckt;
-- Body of the alarm circuit
architecture behav of alarm_ckt is
-- Declarative part
signal secure;
begin
-- Statement part
secure <= window and door and garage; alarm <= panic or (enable and (not exiting) and (not secure); end architecture behav; Figure 4(c). A VHDL model of the alarm circuit shown in 4(a) and 4(b)
The VHDL model shown in Fig 4© comprises of an entity (interface) and its architecture (body). The interface specifies the communication of the model with the external world such as the signals that flow into and out of the black box that is represented by the entity. Note the similarities between the entity and symbolic model shown in Fig 4(a). The body (architecture) describes the details of the digital system and how the output changes to variations of the inputs. Thus there is a clear separation in the VHDL model in the specification and implementation. Specifications provide the function to be implemented (identifier) and how the design should communicate with the external world. For example, the specification of the alarm circuit is the entity description of Figure 4©. A number of solutions are feasible for the alarm specification each trading one or more of the following features: cost, speed, reliability, power, etc. Some other implementations of alarm circuit will be presented in later modules. In the next few sections the details (syntax) of the entity and architecture are provided. New features of VHDL are presented as we continue through these sections.
INTERFACE
The interface of the alarm circuit is repeated below
entity alarm_ckt is
· Port declarations
port (DOOR, WINDOW, GARAGE : in STD_LOGIC;
EXITING, PANIC: in STD_LOGIC;
ALARM : out STD_LOGIC);
library IEEE;
use ieee.std_logic_1164.all;
entity alarm_ckt is
· Port declarations
port
( DOOR, WINDOW: in STD_LOGIC;
GARAGE : in STD_LOGIC;
EXITING, PANIC: in STD_LOGIC;
ALARM : out STD_LOGIC); end entity alarm_ckt;
· Body of the alarm circuit
architecture behav of alarm_ckt is
· Declarative part
signal secure;
begin
· Statement part
secure <= window and door and garage; alarm <= panic or (enable and (not exiting) and (not secure); end architecture behav; end entity alarm_ckt; The interface consists of the entity declaration. The header of the entity declaration starts with the keyword entity, followed by the name of the design entity, and followed by the keyword is. Entity declaration closes with the keyword end, followed by an optional keyword entity, followed by the optional entity name. The entity declaration is terminated by a semicolon. The design entity name is an identifier. An identifier may be of any length and is case insensitive. The first character must be a letter and the last character must not be an underscore and can comprise of alphanumeric characters and underscore ( _ ). Lines beginning with two dashes “—“ are comments. Comments can be placed any where within the VHDL code.
The keyword port is used in port declarations. Port declarations are used to specify the name, mode (direction), and type of signals that flow in/out of the design entity. Three commonly used modes of ports are in (input), out (output), and inout (input/output).The type of the port defines the legal values that are allowed at the port. For the time being we will be restricting to bit, std_logic (0 or 1 as values), and Boolean (TRUE or FALSE) data types.
VHDL is a very strongly typed language. Therefore, the port signals data type must match with the signals assigned to the port.
ARCHITECTURE
Following the interface of the alarm circuit, we will look into the body described following.
· Body of the alarm circuit architecture behav of alarm_ckt is
· Declarative part signal secure;
begin
· Statement part
secure <= window and door and garage; alarm <= panic or (enable and (not exiting) and (not secure); end architecture behav; The header of the body begins with the keyword architecture, followed by the architecture name (identifier), followed by the keyword of, followed by the identifier of the design entity, and followed by the key word is. The last statement of the body consists of the keyword end, followed optionally by the keyword architecture and the identifier of the architecture. The architecture primarily consists of two parts: declarative part and statement part. Declarative part declares the data types of objects that are local to the body. Note once again that VHDL is strongly typed. Therefore, all objects must have their data type declared before they are used in the statements. The declarative part effectively extends the header of the architecture to the keyword begin. LOGIC OPERATIONS AND PRECEDENCE VHDL provides a set of predefined logical operators as described below OPERATOR DEFINITION
and conjunction
or disjunction
not complement
nor complement disjunction
nand complement conjunction
xor exclusive disjunction
xnor complement exclusive disjunction
not is a unary operation where as all other logical operations are all binary. The operators in an expression are executed starting from left to right in the order in which they appear. VHDL operators are evaluated in an order determined by the operator precedence. Operators of higher precedence are evaluated before the lower ones. not operator has a higher precedence over all other operators. All other binary operators have equal precedence (different from Boolean logic). Parentheses can be used to control the operator execution.
CONCURRENCY
The assignment statements used in the VHDL model of Figure 4© are called concurrent signal assignment statements. Unlike the assignments done in software programming languages that get executed in a sequential manner, these VHDL signal assignment statements are executed concurrently. The statements get executed whenever a signal value on the right hand side (RHS) of the assignment statement change. There is no implied or explicit procedural flow of control. To visualize this let us look at the logic circuit implemented by the two assignment statements and given in Figure 4©. Thus the concurrent signal assignment statements mimic the nonprocedural characteristics of hardware; the hardware components operate in parallel and will be active whenever one of the inputs of the component changes. The order in which concurrent signal statements are written has no effect on the order in which they execute.
The signal declaration used in the declaration section of the body of the VHDL model starts with the keyword signal followed by the name (identifier) of the signal and its data type. Unlike ports signals do not have a mode or direction of signal flow. A signal in effect represents a wire used to connect logic components. The next two sections illustrate some of the language elements and their organization. Although this deviates from our scheme of presenting VHDL with a design perspective, it provides a good overall description of the organization of the language.
DESIGN UNITS AND LIBRARIES
VHDL language organization is better described in the pyramid structure shown in Figure 5. At the base of the pyramid are the user defined data types and since VHDL is a strongly typed language this forms the foundation. Objects such as signals hold values for the defined data types. Expressions transform or combine operations with these objects. Typically expressions can be viewed as statements within the model. Statements are contained within design units such as entities and architectures. Finally these design units are contained within libraries.
There are five kinds of design units within the VHDL language and they can be categorized as primary and secondary design units.
· Primary design units
1. Entity
2. Package
3. Configuration
· Secondary design units
1. Architectural Body
2. Package Body
Figure 6 illustrates the process of creating a design unit from a textual VHDL models. All design units are stored in libraries. A VHDL compiling and simulating environment typically has a VHDL analyzer, a source-level debugger, a result viewer, and other utilities. A VHDL design file comprises of one or more design entities or units. VHDL analyzer checks the correctness of syntax of the design file. It compiles the textual VHDL code in an intermediate form that is accepted by the VHDL simulator and/or synthesizer. These compiled design units are stored in a design library. The designer specifies one of the design libraries as the WORK library. The compiled unit is stored in the WORK library. The designer can change the mapping of the WORK library. The design environment also provides a library called STD which consists of two predefined packages: STANDARD and TEXTIO. In addition most of the design environments also provide the IEEE standard library which is based on a nine-valued logic, the IEEE standard 1164.
Once all the design units in a complete design are compiled, a top-level design entity or its configuration file is selected for simulation. If simulations thoroughly verify the functioning of design, the VHDL model can be provided as input to synthesizer. The synthesis tool maps the VHDL functionality onto physical hardware or a possible logic circuit that can be physically built as shown in Figure 7
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