Basics RTL Synthesis

RTL Synthesis
• Synthesis is an automatic method of converting a higher level of abstraction (RTL) to a lower level of abstraction (gate level netlists).
• Synthesis produces technology-specific implementation from technology-independent VHDL description.
• Not all VHDL can be used for synthesis. There are the VHDL subset for synthesis and synthesis style description.
• Synthesis is very sensitive to how the VHDL code is written!
• Gate level net lists are optimized for area, speed, power, or testability.

• The essence of RTL is that you define all the registers in the system and the transfers between those registers that occur on each clock cycle (i.e., the combinational logic).
• Registers are described either:
1. explicitly through component instantiation, or
2. implicitly through inference (following a few simple rules)
• Combinational logic is described by: sequential control statements, subprograms, or concurrent statements.
• RTL synthesis describes the behavior of system at each clock period.
• RTL synthesis is used for synchronous design.

• An RTL architecture can be divided into a data path and control:
– Data path: performs operations on data (i.e., ALU),
– Control: tells data path, memory, etc. what to do.
• The data path flows left to right, whereas the control flows bottom up.
• Critical path: critical timing path in a logical circuit is the longest sensitizable path from primary inputs to primary outputs.
• The critical path in the circuit limits the maximum clock frequency.
• Synthesis tools examine all signal paths and spot the critical path.

It is recommended to use RTL code whenever possible as it provides the following:
1. Readable code
2. Ability to use same code for synthesis and simulation
3. Portable code for migration to different technologies
4. Reusable code for later designs

Verilog

Introduction
Verilog allows us to describe a system based on a structure of wires, gates, registers, and
delays using a systematic language. This language is unlike most other programming languages,
where they read like steps in a recipe. Instead, Verilog is written so that most components
respond in parallel, simultaneously.
First Verilog Program
By using your favorite text processor, you can type in Verilog code to be run using
Verilog and simulated in SignalScan. The simplest type of Verilog code is similar to that found in
Prog.1.
// Prog.1: Simple Verilog Code.
module top();
wire out;
reg a, b;
assign out = a & b;
initial
begin
a = 1'b0;
b = 1'b0;
#10;
a = 1'b0;
b = 1'b1;
#10;
a = 1'b1;
b = 1'b1;
#10;
a = 1'b1;
b = 1'b0;
#10;
$dumpflush;
end
initial
begin
$monitor("a=%b, b=%b, out=%b, time=%t\n", a, b, out, $time);
$dumpfile("top.dump");
$dumpvars(5, top);
end
endmodule

Comments
Let's start by examining the code step by step. The first line is a comment defined by the
two slashes. In any program, anything that follows two slashes is ignored by Verilog.
Modules
Modules are what define components in Verilog. They are remarkably similar to functions
or procedures in other languages because given input, they can produce specific output. The
module shown, top, has no input and output, making it self contained. It will be the first module
evaluated when Verilog is run because of this.
A more general module follows the following form:
module modulename(in1, in2, ..., inout1, ..., out1, ...)
input in1, in2, ...;
inout inout1, ...;
output out1, ...;

endmodule
The modulename can be replaced with any name of the module. Although the inputs,
input/outputs, and outputs can be placed in any order within the module's parameters, it is good
to be consistent where you place them within the list. The keywords, input, inout, and output are
used to define the direction that data can flow through the node named by the parameter. These
keywords are used just like the wire and reg keywords which we'll discuss in more depth later.
The module body or text is a list of expressions that define the system. Modules are always
terminated by the keyword, endmodule.
Defining Wires and Registers
In this example, single bit wires and registers are used, although Verilog allows multi-bit
sized wires (buses) and registers to be defined. Wires, registers, inputs, input/outputs, and
outputs are all defined in the same fashion. The only difference being the keyword used.
input a, b;
output [2:0] out;
wire wire1, wire2, a, b;
wire [7:0] byte;
reg [31:0] wordreg;
A name by itself represents a single bit, or wire node. To produce buses, or larger arrays
of bits, the bracketed expression is placed before the name. [2:0] defines 3 bits, 2 through 0.
[7:0] defines 8 bits, 7 through 0. [31:0] defines 32 bits, 31 through 0.
Registers and wires cannot be used everywhere. In the simple program, out is a wire, and
a and b are registers. This is required because out appears at the left hand side of an assign
expression, and a and b appear at the left hand side of '=' signs in the initial expression.